The invention generally relates to delay circuits which are capable of delaying input signals thereof with desired delay times, and more particularly to a delay circuit in which paths, each having a different amount of delay, is selected to provide a desired delay time for an input signal thereof.
FIG. 1 shows one example of the delay circuit which provides four paths, each of which has a different amount of delay and one of which is selected according to needs. The delay circuit of FIG. 1 is including a register 8, delay elements, selectors 11a to 11d and fixed delay elements 12a to 12c. The selectors are connected together in a cascade-connection manner.
Each selector provides four Inputs and four outputs. Specifically, the selector 11a provides four inputs 301a to 304a and four outputs 311a to 314a, wherein an input signal 31 is directly supplied to the Input 301a while the input signal 31 is indirectly supplied to the other inputs 302a to 304a through delay elements 10a1 to 10a3 respectively. The selector 11b provides four inputs 301b to 304b and four outputs 311b to 314b, wherein the selector 11b is connected to the selector 11a in such a way that the input 301b is directly connected to the output 311a and the other inputs 302b to 304b are connected to the outputs 312a to 314a through delay elements 10b1 to 10b3, respectively. The selector 11c includes four inputs 301c to 304c and four outputs 311c to 314c, wherein the selector 11c is connected to the selector 11b in such a way that the input 301c is directly connected to the output 311b and the other inputs 302c to 304c are connected to the outputs 312b to 314b through delay elements 10c1 to 10c3 respectively. The selector 11d includes four inputs 301d to 304d and four outputs 311d to 314d, wherein the selector 11d is connected to the selector 11c in such a way that the input 301d is directly connected to the output 311c and the other inputs 302d to 304d are connected to the outputs 312c to 314c through delay elements 10d1 to 10d3, respectively. The outputs 311d to 314d of the selector 11d are connected together to provide an output signal 33. In other words, one of the outputs 311d to 314d is selected by the selector 11d to provide the output signal 33 which is a pulse signal.
The delay circuit of FIG. 1 provides four paths, wherein a first path corresponds to connection of the inputs 301a-301d and the outputs 311a-311d; a second path corresponds to connection of the inputs 302a-302d and the outputs 312a-312d; a third path corresponds to connection of the inputs 303a-303d and the outputs 313a-313d; and a fourth path corresponds to connection of the inputs 304a-304d and the outputs 314a-314d. Herein, the second path includes the delay elements 10a1-10d1; the third path includes the delay elements 10a2-10d2; and the fourth path includes the delay elements 10a3-10d3. Total amounts of delay of those paths are set such that total amount of delay of the first path is smaller than that of the second path; total amount of delay of the second path is smaller than that of the third path; and total amount of delay of the third path is smaller than that of the fourth path. Naturally, delay time is measured between leading edges of pulse signals.
FIG. 2 shows internal configuration of the selector `11` which represents the selectors 11a to lid. The selector 11 provides four inputs 301 to 304 and four outputs 311 to 314; and the selector 11 is configured by four AND gates 1 to 4, an 0R gate 5 and a decoder 7. The AND gates 1 to 4 receive the inputs 301 to 304 respectively. In addition, the decoder 7 receives 2-bit delay data `305` so as to provide four outputs which are respectively supplied to the AND gates 1 to 4.
At first, the selector 11 receives the delay data 305 so as to turn one of the four outputs of the decoder 7 to `H` level. Thus, one of the AND gates 1 to 4 is opened. Since the inputs 301 to 304 are respectively supplied to the AND gates 1 to 4, one of them is transmitted through the `opened` AND gate and is supplied to the OR gate 5. So, one of the inputs 301 to 304 is provided through the OR gate 5 as the outputs 311 to 314. In short, the selector 11 is a circuit which selects one of four inputs, each having a different amount of delay, so as to provide the selected one as four outputs.
Next, operations of the delay circuit of FIG. 1 will be described in detail in conjunction with FIG. 2. An input pulse signal 31 is directly supplied to the input 301a of the selector 11a; and it is also supplied to the other inputs 302a to 304a through the delay elements 10a1 to 10a3 respectively. If the selector 11a is configured like the selector 11 of FIG. 2, the input pulse signal 31 is directly supplied to the AND gate 1; and it is also supplied to the other AND gates 2 to 4 through the delay elements 10a1 to 10a3 respectively.
The register 8 receives delay data 32 of n bits so as to provide delay data 305a of 2 bits, which are supplied to the selector 11a. In the selector 11a, the decoder 7 decodes the delay data 305a to select one of the AND gate 1 to 4. If the decoder 7 provides H-level output for the AND gate 4, the input 304a is selected. Then, the selected input 304a is transmitted through the 0R gate 5, so that it is distributed to the outputs 311a to 314a. In other words, a delayed pulse signal, which is delayed behind the input pulse signal 31 by a delay time of the delay element 10a3, is distributed to the outputs 311a to 314a, through which It is outputted to the selector 11b.
If the selector 11b is configured like the selector 11, the delayed pulse signal is directly supplied to the AND gate 1; and it is also supplied to the other AND gates 2 to 4 through the delay elements 10b1 to 10b3 respectively.
If the register 8 delivers delay data 305b to the selector 11b through the fixed delay element 12a, the decoder 7 in the selector 11b decodes the delay data 305b to select one of the AND gates 1 to 4. Thus, one of the inputs 301b to 304b is selectively transmitted through the 0R gate 5 and is distributed to the outputs 311b to 314b.
Operations described above are performed by each of the other selectors 11c and 11d. Thus, a desired combination of the delay elements can be implemented. In other words, arbitrary combination among the delay elements 10a1-10a3, 10b1-10b3, 10c1-10c3 and 10d1-10d3 can be made by the selectors 11a to 11d. Thus, an output pulse signal 33 is delayed behind the input pulse signal 31 by an arbitrary amount of delay which corresponds to the arbitrary combination of the delay elements. In short, total amount of delay of the delay circuit of FIG. 1 can be arbitrarily varied in accordance with built-in programs which are executed by the selectors 11a to 11d.
By the way, the delay circuit of FIG. 1 is designed such that the register 8 delivers delay data 305a to 305d to the selectors 11a to 11d respectively in synchronization with input pulse signal 31 applied to the inputs 301 of the selectors 11a through 11d.
If the fixed delay elements 12a to 12d are removed from the delay circuit of FIG. 1, the register 8 should deliver the delay data 305a to 305d for the selectors 11a to 11d until the selector 11d provides the output pulse signal 33, wherein delivering of the delay data should be made before the next pulse signal 31 is applied to the selector 11a. For this reason, it is not necessary to adjust timings between delay time and a pulse signal which passes through the delay circuit; and consequently, a so-called on-the-fly operation, in which an amount of delay for the pulse signal is varied in real time, cannot be performed at high speed.
In short, if the fixed delay elements 12a to 12c do not exist in the delay circuit of FIG. 1, a repeat period of the input pulse signal 31 cannot be made shorter than a maximum delay time, which is sum of first to fourth times. Herein, the first time is a period of time in which an input pulse signal 31 is transmitted through a maximum delay element, selected from among the delay elements 10a1 to 10a3, and is then outputted from the selector 11a; the second time is a period of time in which an output signal of the selector 11a is transmitted through a maximum delay element among the delay elements 10b1 to 10b3 and is then outputted from the selector 11b; the third time is a period of time in which an output signal of the selector 11b is transmitted through a maximum delay element among the delay elements 10c1 to 10c3 and is then outputted from the selector 11c; and the fourth time is a period of time in which an output signal of the selector 11c is transmitted through a maximum delay element among the delay elements 10d1 to 10d3 and is then outputted from the selector 11d. As a result, a period corresponding to the maximum delay time of the delay circuit of FIG. 1 as a whole should coincide with a maximum delay period of the input pulse signal 31. In short, it is not possible to perform on-the-fly operation at high speed.
For these reasons the fixed delay elements 12a to 12c are introduced into the delay circuit of FIG. 1 so as to perform on-the-fly operation at high speed. In the delay circuit of FIG. 1, the fixed delay element 12a is provided to adjust a minimum delay time which is a period of time by which a pulse signal arrives at selector 11b. That is, propagation time of the fixed delay element 12a is adjusted in such a way that the delay data 305b, from the register 8, are sent to the selector 11b at a timing at which an input pulse signal 31 passes through the input 301a and the output 311a of the selector 11a so that it arrives at input 301b of the selector 11b.
Propagation times of the other fixed delay elements 12b and 12c used for the selectors 11c and 11d respectively are adjusted in a manner similar to that of the fixed delay element 12a described above. Thanks to adjustment of the propagation times of the fixed delay elements 12a to 12c, the delay data 305a to 305d are respectively applied to the selectors 11a to 11d at timings by which a pulse signal is applied respectively to the selectors 11a to 11d and directly without being intervened by the delay elements. Thus, it is not necessary to consider about propagation delay of each of the selectors 11a to 11d. As a result, it is possible to perform on-the-fly operation at high speed.
However, the propagation delay may be naturally deviated due to manufacturing process of circuit elements, variation of temperature and deviation of power-supply voltage. In order to cope with the above, it is necessary to provide a relatively long margin of time in adjustment of the fixed delay elements 12a to 12c. For this reason, it is actually difficult to perform on-the-fly operation at high speed.
FIG. 3 shows another type of the delay circuit which also provides four paths each having a different amount of delay. The delay circuit of FIG. 3 including by the register 8, the selectors 11a to 11d, the fixed delay elements 12a to 12c as well as an OR gate 13, delay elements 14a1 to 14a3, 14b1 to 14b3, 14c1 to 14c3, 14d1 to 14d3 and 14e1 to 14e3.
In FIG. 3, the selector 11a is connected to a signal line which transmits an input pulse signal 31. As for the selector 11d, the output 311d is directly connected to a first input of the OR gate 13; and the other outputs 312d to 314d are respectively connected to other inputs of the OR gate 13 through the delay elements 14e1 to 14e3. An output pulse signal 33 is provided from the OR gate 13.
FIG. 4 shows a configuration of the selector 11 which represents the selectors 11a to 11d in FIG. 3. The selector 11 including a decoder 20, an OR gate 21, which receives the inputs 301 to 304, and AND gates 22 to 25, which provide the outputs 311 to 314, respectively. The decoder 20 decodes the delay data 305 of 2 bits so as to selectively open one of the AND gates 22 to 25.
If a pulse signal is transmitted through any one of the inputs 301 to 304, it is delivered to the AND gates 22 to 25 through the OR gate 21. At this moment, any one of the AND gate 22 to 25 is opened by the decoder 20 which decodes the delay data 305. So, the pulse signal is provided as any one of the outputs 311 to 314 by means of the `opened` AND gate. In short, the selector 11 is a circuit which receives one input so as to provide one output onto one of four paths.
Next, operations of the delay circuit of FIG. 3 will be described in conjunction with FIG. 4. At first, an input pulse signal 31 is applied to the selector 11a. For example, if the register 8 supplies the delay data 305a to the selector 11a wherein the delay data 305a are at `H` level, the selector 11a selects the output 314a. So, the pulse signal, which is provided from the output 314a of the selector 11a, is transmitted to the input 304b of the selector 11b through the delay element 14a3.
The selector 11b receives the delay data 305b to select one of the outputs 311b to 314b. If the output 311b is selected, a delayed pulse signal, which is delayed behind the input pulse signal 31 by delay time of the delay element 14a3, is directly transmitted to the input 301c of the selector 11c. If the output 312b is selected, the delayed pulse signal is transmitted to the input 302c of the selector 11c through the delay element 14b1. In other words, the input 302c of the selector 11c receives a delayed pulse signal which is delayed behind the input pulse signal 31 by sum of delay times of the delay elements 14a3 and 14b1. If the output 313b is selected, the input 303c of the selector 11c receives a delayed pulse signal which is delayed behind the input pulse signal 31 by sum of delay times of the delay elements 14a3 and 14b2. If the output 314b is selected, the input 304c of the selector 11c receives a delayed pulse signal which is delayed behind the input pulse signal 31 by sum of delay times of the delay elements 14a3 and 14b3.
A similar manner of selection is conducted on the outputs of the selectors 11c and 11d. So, an output pulse signal 33, which is outputted from the 0R gate 13, has a total delay time which corresponds to combination of the delay elements arbitrarily selected from among the delay elements 14a1-14a3, 14b1-14b3, 14c1-14c3, 14d1-14d3 and 14e1-14e3. In other words, it is possible to change the total delay time in a programmable way by setting an arbitrary combination of the delay elements.
The delay circuit of FIG. 3 is designed such that the register 8 sends out the delay data 305a to 305d for the selectors 11a to 11d respectively in synchronization with input pulse signal 31 applied to the selector 11a. Because of the reasons described before, the fixed delay elements 12a to 12c are provided to enable on-the-fly operation.
Now, propagation time of the fixed delay element 12a is adjusted in such a way that delay data 305b, from the register 8, is applied to the selector 11b by a minimum delay time for the pulse signal to reach the selector 11b; in other words, the propagation time is adjusted such that the delay data 305b are applied to the selector 11b at a time at which the input pulse signal 31 arrives at input 301b of the selector 11b.
The other fixed delay elements 12b and 12c, provided for the selectors 11c and 11d respectively, are adjusted in a similar way. Adjustment of the fixed delay elements 12a to 12c allows the delay data 305a to 305d to arrive at selectors 11a to 11d respectively in synchronization with timings by which the pulse signal is directly transmitted to the selectors 11a to 11d respectively without being Intervened by the delay elements. Thus, it is not necessary to consider about propagation delay of each of the selectors 11a to 11d; and consequently, it is possible to perform on-the-fly operation at high speed.
However, the aforementioned deviation may actually occur in the propagation delay because of the manufacturing process of circuit elements, variation of temperature and deviation of power-supply voltage. So, it is necessary to provide a relatively long margin of time in adjustment of the fixed delay elements 12a to 12c. Therefore, even in the delay circuit of FIG. 3, it is difficult to perform on-the-fly operation at high speed.